C

Calculating and Fixing Process Antenna Violations

This appendix describes process antenna violations and how you can use the router to correct them. It includes the following sections:

Overview

Using Process Antenna Keywords in the LEF and DEF Files

Calculating Antenna Ratios

Checking for Antenna Violations

Using Antenna Diode Cells

Using DiffUseOnly

Calculations for Hierarchical Designs

Overview

During deep submicron wafer fabrication, gate damage can occur when excessive static charges accumulate and discharge, passing current through a gate. If the area of the layer connected directly to the gate or connected to the gate through lower layers is large relative to the area of the gate and the static charges are discharged through the gate, the discharge can damage the oxide that insulates the gate and cause the chip to fail. This phenomenon is called the process antenna effect (PAE).

To determine the extent of the PAE, the router calculates the area of the layer relative to the area of the gates connected to it, or connected to it through lower layers. The number it calculates is called the antenna ratio. Each foundry sets a maximum allowable antenna ratio for the chips it fabricates.

For example, assume a foundry sets a maximum allowable antenna ratio of 500. If a net has two input gates that each have an area of 1 square micron, any metal layers that connect to the gates and have an area larger than 1,000 square microns have process antenna violations because they would cause the antenna ratio to be higher than 500:

To tell the router the values to use when it calculates the antenna ratio, you set antenna keywords in the LEF and DEF files. The router measures potential damage caused by PAE by checking the ratio it calculates against the values specified by the antenna keywords. When it finds a net whose antenna ratio for a specified layer exceeds the maximum allowed value for that layer, it finds a process antenna violation and attempts to fix it using one or both of the following methods:

Changing the routing so the routing layers connected to a gate or connected to a gate through lower layers are not so large that they build enough static charge to damage the gate

Inserting diodes that protect the gate by providing an alternate path to discharge the static charge

LEF can specify several types of antenna ratios, including ratios for PAE damage on one layer only and ratios calculated by adding accumulated damage on several layers. In addition, LEF can specify ratios based on the area of the metal wires or the cut area of vias.

What Are Process Antennas?

In a chip manufacturing process, metal layers are built up, layer by layer, starting with the first-level metal layer (usually referred to as metal1). Next, the metal1-metal2 vias are created, then the second-level metal layer, then metal2-metal3 vias, and so on.

On each metal layer, metal is initially deposited so it covers the entire chip. Then, the unneeded portions of the metal are removed by etching, typically in plasma (charged particles).

Figure C-1 shows a section of an imaginary chip after the unneeded metal from metal2 is removed.

Figure C-1

In the figure,

Gate areas for transistors are labelled G_k, where k is a sequential number starting with 1.

Wire segments are labelled N_i,j

N signifies that the wire segment is an electrically connected node

i specifies the metal layer to which the node belongs

j is a sequential number for the node on that metal layer

Nodes are labelled so that all pieces of the metal geometry on layer metal_i that are electrically connected by conductors at layers below metal_i belong to the same node. For example, the two metal2 wire segments that belong to node N_2,1 are electrically connected to gates G₁, G_2, and G₃ by a piece of wire on metal1 (labelled N_1,2).

Thick oxide insulates the already-fabricated structures below metal2, preventing them from direct contact with the plasma. The metal2 geometries, however, are exposed to the plasma, and collect charge from it. As the metal geometries collect charge, they build up voltage potential.

Because the metal geometries collect charge during the metallization process, they are referred to as process antennas. In general, the more area covered by the metal geometries that are exposed to the plasma (that is, the larger the process antennas), the more charge they can collect.

In Figure C-1 , note the following:

Node N_1,1 is electrically connected to gates G₁ and G₂.

Node N_1,2 is electrically connected to gate G₃.

Node N_2,1 (node N_2,1 has two pieces of metal) is electrically connected to gates G₁, G₂, and G₃.

Node N_1,3 and node N_2,2 are electrically connected to gate G₄.

Node N_1,4 and node N_2,3 are electrically connected to the diffusion (diode).

What Is the Process Antenna Effect (PAE)?

If the voltage potential across the gate oxide becomes large enough to cause current to flow across the gate oxide, from the process antennas to the gates to which the process antennas are electrically connected, the current can damage the gate oxide. The process antenna effect (PAE) is the term used to describe the build-up of charge and increase in voltage potential. The larger the total gate area that is electrically connected to the process antennas on a specific layer, the more charge the connected gates can withstand.

In the imaginary chip in Figure C-1 , if the current were to flow, the following would happen, as a result of the node-gate connections:

The charge collected by process antennas on nodes N_1,1, N_1,2, and N_2,1 would be discharged through one or more of gates G₁, G₂, and G₃.

The charge collected by process antennas on nodes N_1,3 and N_2,2 would be discharged through gate G₄.

The charge collected by process antennas on node N_1,4 and N_2,3 would be discharged through the diode.

What Is the Antenna Ratio?

Because the total gate area that is electrically connected to a node (and therefore connected to the process antennas) determines the amount of charge from the process antennas the electrically connected gates can withstand, and because the size of the process antennas connected to the node determines how much charge the antennas collect, it is useful to calculate the ratio of the size of the process antennas on a node to the size of the gate area that is electrically connected to the node. This is the antenna ratio. The greater the antenna ratio, the greater the potential for damage to the gate oxide.

If you check a chip and obtain an antenna ratio greater than the threshold specified by the foundry, gate damage is likely to occur.

Figure C-2 shows the same section of the imaginary chip as the previous figure. The shaded areas in this figure represent the process antennas on node N_2,1 and the gates to which they connect: gates G₁, G₂, and G₃. The shaded gates discharge the electricity collected by the process antennas on node N_2,1.

Figure C-2

What Can Be Done to Improve the Antenna Ratio?

If there is an alternate path for the current to flow, the charge on the node can be discharged through the alternate path before the voltage potential reaches a level that damages the gate. For example, a Zener diode, which allows current to flow in the reverse direction when the reverse bias reaches a specified breakdown voltage, provides an alternate path, and helps avoid building up so much charge at the node that the charge is discharged through the gate oxide. Diffusion features that form the output of a logic gate (source and drain of transistors) can provide such an alternate discharge path.

Routers typically use two methods to decrease the antenna ratio:

Changing the routing by breaking the metal layers into smaller pieces

Inserting antenna diode cells to discharge the current

Both of these methods supply alternate paths for the current. For details about how to specify antenna diode cells, see "Using Antenna Diode Cells".

Using Process Antenna Keywords in the LEF and DEF Files

You tell the router the values to use for the gate, diffusion, and metal areas by setting values for process antenna keywords in the LEF and DEF files for your design. You also tell the router the values to use for the threshold process antenna ratios by setting the keywords.

The following table lists LEF version 5.5 antenna keywords.


If the keyword ends with ...	It refers to ...	Examples
area	Area of the gates or diffusion Measured in square microns	ANTENNADIFFAREA ANTENNAGATEAREA
factor	Area multiplier used for the metal nodes	ANTENNAAREAFACTOR ANTENNASIDEAREAFACTOR Note: Use DIFFUSEONLY if you want the multiplier to apply only when connecting to diffusion. For more information, see "Using DiffUseOnly".
ratio	Relationship the router is calculating Cum is used in keywords for cumulative antenna ratio.	ANTENNAAREARATIO ANTENNASIDEAREARATIO ANTENNADIFFAREARATIO ANTENNADIFFSIDEAREARATIO ANTENNACUMAREARATIO ANTENNACUMSIDEAREARATIO ANTENNACUMDIFFAREARATIO ANTENNACUMDIFFSIDEAREARATIO

Calculating Antenna Ratios

Tools should calculate antenna ratios using one of the following models:

The partial checking model

Using this model, you calculate damage to gates by process antennas on one layer. For example, if you use the partial checking model to calculate the PAE referred to a gate from metal3, you do not consider any potential damages referred to that gate from metallization steps on metal1 or metal2.

You use this model to calculate a partial antenna ratio (PAR). A PAR tells you if any single metallization step is likely to inflict damage to a gate.

The cumulative checking model

This model is more conservative than the partial checking model. It adds damage to a gate caused by the PAE referred to the gate from each metallization step, starting from metal1 up to the layer that is being checked. For example, if you use the cumulative checking model to calculate the PAE referred to a gate from metal3, you add the PAR from the relevant antenna areas on metal1, metal2, and metal3.

You use this model to calculate a cumulative antenna ratio (CAR). A CAR adds the damages on successive layers together to accumulate them as the layers are built up.

Calculating the Antenna Area

The area used to model the charge-collecting ability of a node is called the antenna area. The router calculates the antenna area for one of the following areas:

The drawn area (the top surface area of the metal shape)

The side area (the area of the sides of the metal shape)

The height of each side is taken from the THICKNESS statement for that layer.

Figure C-3 shows drawn and side areas.

Figure C-3

Antenna Area Factor

You can increase or decrease the calculated antenna area by specifying an antenna area factor in the LEF file.

Use ANTENNAAREAFACTOR to adjust the calculation of the drawn area.

Use ANTENNASIDEAREAFACTOR to adjust the calculation of the side area.

The default value of both factors is 1.

The final ratio check can be scaled (that is, made more or less pessimistic) by using the ANTENNAAREAFACTOR or ANTENNASIDEAREAFACTOR values that are used to multiply the final PAR and CAR values.

Note: The LEF and DEF ANTENNA values are always unscaled values; only the final ratio-check is affected by the scale factors.

Calculating a PAR

The general PAR(m₁) equation for a single layer is calculated as:

The existing ANTENNAAREAFACTOR statement is shown as metalFactor for the metal area. It has no effect on the diff_area, gate_area, or cut_area shown. Likewise, the ANTENNAAREADIFFREDUCEPWL statement is shown as diffMetalReduceFactor, the ANTENNAAREAMINUSDIFF statement is shown as minusDiffFactor, and the ANTENNAGATEPLUSDIFF statement is shown as plusDiffFactor. For cut layer, the ratio equation illustrates the effect of an ANTENNAAREAFACTOR cutFactor statement as metalFactor. If there is no preceding ANTENNAAREAFACTOR statement, the metalFactor value defaults to 1.0.

For single layer rules, the PAR value is compared to ANTENNA[SIDE]AREARATIO and/or ANTENNADIFF[SIDE]AREARATIO, as appropriate. For cumulative layer rules, the CAR values is compared to ANTENNACUM[SIDE]AREARATIO and/or ANTENNACUMDIFF[SIDE]AREARATIO, as appropriate.

The following example uses a simplified formula to calculate a PAR, without including the various area factors:

PAR(N_i_,_j, G_k) is the partial antenna ratio for node j on metal_i with respect to gate G_k, where G_k is electrically connected to node N_i_,_j by layer i or below.

Area(N_i_,_j) is the drawn or side area of node N_i_,_j.

C(N_i_,_j) is the set of gates G_k that are electrically connected to N_i_,_j through the layers below metal_i.

Area(G_k) is the drawn or side area of gate G_k. (The reason to include the G_k parameter for PAR is to maintain uniformity with the notation for CAR.)

Note: For a specified node N_i_,_j, the PAR(N_i_,_j, G_k) for all gates G_k that are connected to the node N_i_,_j using metal_i or below are identical.

Calculations for PAR on the First Metal Layer

Figure C-4 shows a section of an imaginary chip after the first metal layer is processed.

Figure C-4

To calculate PAR(N_i_,_j, G_k) for node N_1,1, a node on the first metal layer, with respect to gate G₁, use the following formula:

Because gates G₁ and G₂ both connect to node N_1,1, the following statement is true:

PAR(N_1,1,G₁) = PAR(N_1,1,G₂)

To calculate PAR for node N_1,2, another node on the first metal layer, with respect to gate G₃, use the following formula:

To calculate PAR(N_i_,_j, G_k) for node N_1,3, another node on the first metal layer, with respect to gate G₄, use the following formula:

Calculations for PAR on the Second Metal Layer

Figure C-5 shows the chip after the second metal layer is processed.

Figure C-5

N_2,1 consists of two pieces of metal on the second layer that are electrically connected at this step in the fabrication process. Therefore, to calculate PAR(N_2,1,G₁), you must add the area of both pieces together.

To calculate PAR(N_i_,_j,G_k) for node N_2,1, a node on the second metal layer, with respect to gate G₁, use the following formula:

As on the first layer,

PAR(N_2,1,G₁) = PAR(N_2,1,G₂) = PAR(N_2,1,G₃)

Calculations for PAR on the Third Metal Layer

Figure C-6 shows the chip after the third metal layer is processed.

Figure C-6

To calculate PAR(N_i_,_j, G_k)for node N_3,1, a node on the third metal layer, with respect to gate G₁, use the following formula:

As on the prior layers,

PAR(N_3,1,G₁) = PAR(N_3,1,G₂) = PAR(N_3,1,G₃) = PAR(N_3,1,G₄)

Calculations for PAR on the Fourth Metal Layer

Figure C-7 shows the chip after the fourth metal layer is processed.

Figure C-7

To calculate PAR(N_i,_j, G_k) for the fourth metal layer, use the following formula:

As on the prior layers,

PAR(N_4,1,G₁) = PAR(N_4,1,G₂) = PAR(N_4,1,G₃) = PAR(N_4,1,G₄)

Note: Node N_4,1 is connected to the diffusion layer through the output diode. After the router calculates the antenna ratio, it compares its calculations to the area of the diffusion, instead of the area of the gates.

Calculating a CAR

To calculate a CAR, the router adds the PARs for all the relevant nodes on the specified or lower metal layers that are electrically connected to a gate. Therefore, CAR(N_i,_j,G_k) designates the cumulative damage to gate G_k by metallization steps up to the current level of metal, i.

To create a single accumulative model that combines both metal and cut damage into one model, specify the ANTENNACUMROUTINGPLUSCUT statement for the layer, so that:

CAR(m_i) = PAR(m_i) + CAR(v_i-1)

This means that the CAR from the cut layer below this metal layer is accumulated, instead of the CAR from the metal layer below this metal layer.

Note: In practice, the router only needs to keep track of the worst-case CAR; however, the CARs for all of the gates shown in Figure C-8 are described here.

The router calculates an antenna ratio with respect to a node-gate pair. To find the CAR for the node N_i,_j - gate G_k pair, you trace the path of the current between gate G_k and node N_i,_j and add the PAR with respect to gate G_k for the all nodes in the path between the first metal layer and layer i that you can trace back to G_k.

Figure C-8

In Figure C-8 , node N_1,2 is not shaded because it was not electrically connected to G₂ when metal1 was processed. That is, because the charge accumulated on N_1,2 when metal1 was processed cannot damage gate G₁, the router does not include it in the calculations for CAR(N_2,1,G₁).

Another way to explain this is to say that the PAE from node N_1,2 with respect to gate G₂ is 0.

Calculations for CAR on the First Metal Layer

Figure C-9 shows the chip after the first metal layer is processed.

Figure C-9

In the figure above,

CAR(N_1,1,G₁) = PAR(N_1,1,G₁)

CAR(N_1,1,G₂) = PAR(N_1,1,G₂)

Because PAR(N_1,1,G₁) equals PAR(N_1,1,G₂), CAR(N_1,1,G₁) equals CAR(N_1,1,G₂).

Note: In general, CAR(N_i,j,G_k) equals CAR(N_i,j,G_k') if the two gates G_k and G_k' are electrically connected to the same node on metal1, the lowest layer that is subject to the process antenna effect.

Calculations for CAR on the Second Metal Layer

Figure C-10 shows the chip after the second metal layer is processed.

Figure C-10

In the figure above, N_1,2 is not included in the calculations for CAR(N_2,1,G₁) because it was not electrically connected to G₁ when metal1 was processed. That is, because the charge accumulated on N_1,2 when metal1 was processed cannot damage gate G₁, the router does not include it in the calculations for CAR(N_2,1,G₁).

In the figure above,

CAR(N_2,1,G₁) = PAR(N_1,1,G₁) + PAR(N_2,1,G₁)

CAR(N_2,1,G₂) = PAR(N_1,1,G₂) + PAR(N_2,1,G₂)

Gates G₁ and G₂ have the same history with regard to PAE because they are connected to the same piece of metal1, so they have the same CAR for any node on a specified layer:

CAR(N_2,1,G₁) = CAR(N_2,1,G₂)

Calculations for CAR on the Third Metal Layer

Figure C-11 shows the chip after the third metal layer is processed.

Figure C-11

Gate G₁

In the figure above,

CAR(N_3,1,G₁) = PAR(N_1,1,G₁) + PAR(N_2,1,G₁) + PAR(N_3,1,G₁)

Gate G₂

In the figure above,

CAR(N_3,1,G₂) = PAR(N_1,1,G₂) + PAR(N_2,1,G₂) + PAR(N_3,1,G₂)

CAR(N_3,1,G₁) equals CAR(N_3,1,G₂) because gates G₁ and G₂ are both electrically connected to the same node, N_1,1, on metal1 and therefore have the same history with regard to PAE. Therefore, the formula for CAR(N_3,2, G₂) is CAR(N_3,1,G₁) = CAR(N_3,1,G₂)

Gates G₃ and G₄

Gates G₃ and G₄ are not connected to the same node on metal1 and therefore do not have the same history with regard to PAE. Therefore, the CAR(N_3,1,G₃) and CAR(N_3,1,G₄) do not necessarily equal CAR(N_3,1,G₁) or CAR(N_3,1,G₂).

In Figure C-12 , the relevant areas for calculating CAR for gate G₃ are shaded.

Figure C-12

In the figure above,

CAR(N_3,1,G₃) = PAR(N_1,2,G₃) + PAR(N_2,1,G₃) + PAR(N_3,1,G₃)

In Figure C-13 , the relevant areas for calculating CAR for gate G₄ are shaded.

Figure C-13

In the figure above,

CAR(N_3,1,G₄) = PAR(N_1,3,G₄) + PAR(N_2,2,G₄) + PAR(N_3,1,G₄)

Calculations for CAR on the Fourth Metal Layer

The following figure shows the chip after the fourth metal layer is processed.

Gates G₁ and G₂

In Figure C-14 , the relevant areas for calculating CAR(N_4,1,G₁) and CAR(N_4,1,G₂) are shaded.

Figure C-14

In the figure above,

CAR(N_4,1,G₁) = PAR(N_1,1,G₁) + PAR(N_2,1,G₁)
+ PAR(N_3,1,G₁) + PAR(N_4,1,G₁)

CAR(N_4,1,G₂) = PAR(N_1,1,G₂) + PAR(N_2,1,G₂)
+ PAR(N_3,1,G₂) + PAR(N_4,1,G₂)

CAR(N_4,1,G₁) = CAR(N_4,1,G₂)

Gate G₃

In Figure C-15 , the relevant areas for calculating CAR(N_4,1,G₃) are shaded.

Figure C-15

In the figure above,

CAR(N_4,1,G₃) = PAR(N_1,2,G₃) + PAR(N_2,1,G₃)
+ PAR(N_3,1,G₃) + PAR(N_4,1,G₃)

CAR(N_4,1,G₃) does not equal CAR(N_4,1,G₁) or CAR(N_4,1,G₂) because it is not connected to the same node on metal1.

Gate G₄

In Figure C-16 , the relevant areas for calculating CAR(N_4,1,G₄) are shaded.

Figure C-16

In the figure above,

CAR(N_4,1,G₄) = PAR(N_1,3,G₄) + PAR(N_2,2,G₄)
+ PAR(N_3,1,G₄) + PAR(N_4,1,G₄)

CAR(N_4,1,G₄) does not equal CAR(N_4,1,G₁), CAR(N_4,1,G₂), or CAR(N_4,1,G₃) because it is not connected to the same node on metal1.

Calculating Ratios for a Cut Layer

The router calculates damage from a cut layer separately from damage from a metal layer. Calculations for the cut layers do not use side area modelling.

Calculating a PAR on a Cut Layer

The general PAR(c_i) equation for a single layer is calculated as:

The existing ANTENNAAREAFACTOR statement is shown as cutFactor for the metal area. Likewise, the ANTENNAAREADIFFREDUCEPWL statement is shown as diffAreaReduceFactor, the ANTENNAAREAMINUSDIFF statement is shown as minusDiffFactor, and the ANTENNAGATEPLUSDIFF statement is shown as plusDiffFactor. For cut layer, the ratio equation illustrates the effect of an ANTENNAAREAFACTOR cutFactor statement as metalFactor. If there is no preceding ANTENNAAREAFACTOR statement, the metalFactor value defaults to 1.0.

In the figures and text that follow,

Cij is the cut layer between metal_i and metal_j.

N_C_ij_,_k specifies an electrically connected node on Cij.

The nodes are numbered sequentially, from left to right.

Figure C-17 shows the chip after the C12 process step.

Figure C-17

In the figure above,

As in calculations on the metal layers,

PAR(N_C12,1,G₁) = PAR(N_C12,1,G₂)

Calculating a CAR on a Cut Layer

As explained in "Calculating Antenna Ratios":

CAR(c_i) = PAR(c_i) + CAR(c_i-1)

To create a single accumulative model that combines both metal and cut damage into one model, specify the ANTENNACUMROUTINGPLUSCUT statement for the layer, so that:

CAR(c_i) = PAR(c_i) + CAR(m_i-1)

This means that the CAR from the metal layer below this cut layer is accumulated, instead of the CAR from the cut layer below this cut layer.

Figure C-18 shows the chip after the C23 process step.

Figure C-18

The router calculates the CAR with respect to gate G₃ after the cut C23 process step as follows:

Figure C-19 shows the chip after the C34 process step.

Figure C-19

The router calculates the CAR with respect to gate G₃ after the cut C34 process step as follows:

Checking for Antenna Violations

For each metal layer, the router performs several antenna checks, using the keywords and values specified in the LEF or DEF file. The router can perform the following four types of antenna checks, depending on the keywords you set in the LEF file:

Area Ratio Check

Side Area Ratio Check

Cumulative Area Ratio Check

Cumulative Side Area Ratio Check

Area Ratio Check

The area ratio check compares the PAR for each layer to the value of the ANTENNAAREARATIO or ANTENNADIFFAREARATIO.

The router calculates the PAR as follows:

According to the formula above, the area ratio check finds the PAR for node N_i,j with respect to gate G_k by dividing the drawn area of the node by the area of the gates that are electrically connected to it. The final PAR is multiplied by the ANTENNAAREAFACTOR (the default value for the factor is 1) and compared to the ANTENNAAREARATIO or ANTENNADIFFAREARATIO. If the PAR is greater than the ANTENNAAREARATIO or ANTENNADIFFAREARATIO specified in the LEF file, the router finds a process antenna violation and attempts to fix it.

The link between PAR(N_i,j,G_k) and a PAE violation at node N_i,j depends on whether node N_i,j is connected to a piece of diffusion, as follows:

If there is no connection from node N_i,jto a diffusion area through the current and lower layers, a violation occurs when the PAR is greater than the ANTENNAAREARATIO.

If there is a connection from node N_i,jto a diffusion area through current and lower layers, a violation occurs when the PAR is greater than the ANTENNADIFFAREARATIO.

If there is a connection from node N_i,jto a diffusion area through current and lower layers, and ANTENNADIFFAREA is not specified for an output or inout pin, the value is 0.

Side Area Ratio Check

The side area ratio check compares the PAR computed based on the side area of the nodes for each layer to the value of the ANTENNASIDEAREARATIO or ANTENNADIFFSIDEAREARATIO.

The router calculates the PAR as follows:

According to the formula above, the area ratio check finds the PAR for node N_i,j with respect to gate G_k by dividing the side area of the node by the area of the gates that are electrically connected to N_i,j. The final PAR is multiplied by the ANTENNASIDEAREAFACTOR (the default value for the factor is 1) and compared to the ANTENNASIDEAREARATIO or ANTENNADIFFSIDEAREARATIO. If the PAR is greater than the ANTENNASIDEAREARATIO or ANTENNADIFFSIDEAREARATIO specified in the LEF file, the router finds a process antenna violation and attempts to fix it.

The link between PAR(N_i,j,G_k) and a PAE violation at node N_i,j depends on whether node N_i,j is connected to a piece of diffusion, as follows:

If there is no connection to the diffusion area through the current and lower layers, a violation occurs when the PAR is greater than the ANTENNASIDEAREARATIO.

If there is a connection to the diffusion area through current and lower layers, a violation occurs when the PAR is greater than the ANTENNADIFFSIDEAREARATIO.

If there is a connection to the diffusion area through current and lower layers, and ANTENNADIFFAREA is not specified for an output or inout pin, the value is 0.

Cumulative Area Ratio Check

The cumulative area ratio check compares the CAR to the value of ANTENNACUMAREARATIO or ANTENNACUMDIFFAREARATIO. The CAR is equal to the sum of the PARs of all nodes on the same or lower layers that are electrically connected to the gate.

Note: When you use CARs, you can ignore metal layers by not specifying the CAR keywords for those layers. For example, if you want to check metal1 using a PAR and the remaining metal layers using a CAR, you can define ANTENNAAREARATIO or ANTENNASIDEAREARATIO for metal1, and ANTENNACUMAREARATIO or ANTENNACUMSIDEAREARATIO for the remaining metal layers.

The cumulative area ratio check finds the CAR for node N_i,j with respect to gate G_k by adding the PARs for all layers of metal, from the current layer down to metal1, for all nodes that are electrically connected G_k. The final CAR is multiplied by the ANTENNAAREAFACTOR (the default value for the factor is 1) and compared to the ANTENNACUMAREARATIO or ANTENNACUMDIFFAREARATIO. If the CAR is greater than the ANTENNACUMAREARATIO or ANTENNACUMDIFFAREARATIO specified in the LEF file, the router finds a process antenna violation and attempts to fix it.

The link between CAR(N_i,j,G_k) and a PAE violation at node N_i,j depends on whether node N_i,j is connected to a piece of diffusion, as follows:

If there is no connection to a diffusion area through the current and lower layers, a violation occurs when the CAR is greater than the ANTENNACUMAREARATIO.

If there is a connection to a diffusion area through current and lower layers, a violation occurs when the CAR is greater than the ANTENNACUMDIFFAREARATIO.

If there is a connection to a diffusion area through current and lower layers, and ANTENNADIFFAREA is not specified for an output or inout pin, the value is 0.

Cumulative Side Area Ratio Check

The cumulative side area ratio check compares the CAR to the value of the ANTENNACUMSIDEAREARATIO or ANTENNACUMDIFFAREARATIO.

The cumulative side area ratio check finds the CAR for node N_i,j with respect to gate G_k by adding the PARs for all layers of metal, from the current layer down to metal1, for all nodes that are electrically connected G_k. The final CAR is multiplied by the ANTENNASIDEAREAFACTOR (the default value for the factor is 1) and compared to the ANTENNACUMSIDEAREARATIO or ANTENNACUMDIFFAREARATIO. If the CAR is greater than the ANTENNACUMSIDEAREARATIO or ANTENNACUMDIFFAREARATIO specified in the LEF file, the router finds a process antenna violation and attempts to fix it.

If there is no connection to a diffusion area through the current and lower layers, a violation occurs when the CAR is greater than the ANTENNACUMSIDEAREARATIO.

If there is a connection to a diffusion area through current and lower layers, a violation occurs when the CAR is greater than the ANTENNACUMSIDEAREARATIO.

If there is a connection to a diffusion area through current and lower layers, and ANTENNACUMDIFFAREA is not specified for an output or inout pin, the value is 0.

Cut Layer Process Antenna Model Examples

Example 1

To create the following process antenna rule for a cut layer via1:

cut_area / (gate_area + 2.0 x diff_area) <= 10

Cut layers should include the following information:

ANTENNAGATEPLUSDIFF 2.0 ;

ANTENNADIFFAREARATIO 10 ;

Example 2

Assume the following process antenna rule:

cut_area x PWL(diff_area) / gate_area <= 10

This rule uses a cumulative model with diffusion area reduction function, where:

PAR = (cut_area x diffReduceFactor) / gate_area <= 10

diffReduceFactor = 1.0 for diff_area < 0.1μm²

diffReduceFactor = 0.2 for diff_area >= 0.1 μm²

Cut layers should include the following information:

ANTENNAAREADIFFREDUCEPWL ( ( 0.0 1.0 ) ( 0.0999 1.0 ) ( 0.1 0.2 )

( 1000.0 0.2 ) ) ;

ANTENNACUMDIFFAREARATIO 10 ;

For examples of models that use the ANTENNACUMROUTINGPLUSCUT and the ANTENNAAREAMINUSDIFF rules, see the examples below in "Routing Layer Process Antenna Models."

Routing Layer Process Antenna Model Examples

The following process antenna rule examples use the topology shown in Figure C-20 . In this figure, there are two polysilicon gates (G1, G2), one diffusion connection (D1), contacts (C), and via (V1, V2) and metal (M1, M2, M3) shapes. Note that M1,2 is one LEF PIN, and M1,3 is a different LEF PIN. The other metal is routing.

Figure C-20

The following area values are also used for the examples:


G1 = 1.0	D1 = 0.5	M2,1 = 4.0
G2 = 2.0	M1,1 = 1.0	M2,2 = 5.0
All Cs = 0.1	M1,2 = 2.0	M3,1 = 6.0
All Vs = 0.1	M1,3 = 3.0	M3,2 = 9.0

Example 1

The following process antenna rule combines cut area and metal area into one cumulative rule:

ratio = (metal _area + 10 x cut_area) / gate_area

The cumulative ratio <= 1000 for diffusion < 0.1, and <= 4000 for diffusion >= 0.1

The single layer ratio <= 500 for diffusion < 0.1, and <= 1500 for diffusion >= 0.1

Every routing layer should include the following information:

ANTENNACUMROUTINGPLUSCUT ;

ANTENNACUMDIFFAREARATIO ( ( 0.0 1000 ) ( 0.0999 1000 ) ( 0.1 4000 )

( 1000.0 4000 ) ) ;

ANTENNADIFFAREARATIO ( ( 0.0 5000 ) ( 0.0999 500 ) ( 0.1 1500 )

( 1000.0 1500 ) ) ;

Every cut layer should include the following information:

ANTENNAAREAFACTOR 10 ; #10.0 x cut area

ANTENNACUMROUTINGPLUSCUT ;

ANTENNACUMDIFFAREARATIO ( ( 0.0 1000 ) ( 0.0999 1000 ) ( 0.1 4000 )

( 1000.0 4000 ) ) ;

ANTENNADIFFAREARATIO ( ( 0.0 5000 ) ( 0.0999 500 ) ( 0.1 1500 )

( 1000.0 1500 ) ) ;

Note: ANTENNAAREARATIO and ANTENNACUMAREARATIO are not required because the *DIFFAREARATIO statements are checked, even if diff_area is equal to 0.

For gate G1, the PARs and CARs are computed as follows:

1.	CAR(C,G1) = 10 x area(C1) / area(G1) = 10 x 0.1 / 1.0 = 1.0

The polysilicon and contact cut layer and shapes are not normally visible in LEF and DEF. If the contact cut area should be included, its CAR value should be included with LEF PIN A, using appropriate ANTENNA statements. The M1 PIN area should not be included because M1 area is a PIN shape in the LEF and will be added in by tools reading LEF. Therefore, there should be two antenna statements for LEF PIN A, either:

ANTENNAGATEAREA 1.0 LAYER M1 ;

ANTENNAMAXCUTCAR 1.0 LAYER C ;

or:

ANTENNAGATEAREA 1.0 LAYER M1 ;

ANTENNAMAXAREACAR 1.0 LAYER M1 ;

Because the M1 PIN area is not included in the MAXAREACAR value, both of sets of statements give the same results. For more details, see "Calculations for Hierarchical Designs."

Similarly, the LEF PIN B should have values, such as either:

ANTENNAGATEAREA 2.0 LAYER M1 ;

ANTENNADIFFAREA 0.5 LAYER M1 ;

ANTENNAMAXCUTCAR 1.0 LAYER C ; #only C2 affects G2; C3 does not

or:

ANTENNAGATEAREA 2.0 LAYER M1 ;

ANTENNADIFFAREA 0.5 LAYER M1 ;

ANTENNAMAXAREACAR 1.0 LAYER M1 ; #only C2 affects G2; C3 does not

2.	PAR(M1,G1) = area(M1,2) / area(G1) = 2 / 1 = 2.0

3.	CAR(M1,G1) = PAR(M1,G1) + PIN A's CAR(C,G1) PIN A's CAR(C,G1) = ANTENNAMAXCUTCAR for LAYER C = 1.0 = 2.0 + 1.0 = 3.0

4.	diode_area = 0, single-layer PWL(0) = 500, check PAR(M1,G1) = 2.0 <= 500, cum-layer PWL(0) = 1000, therefore check CAR(M1,G1) = 3.0 <= 1000

5.	PAR(V1,G1) = 10 x area(V1,2 + V1,3) / area(G1) = 10 x 0.2 / (1) = 2.0

6.	CAR(V1,G1) = PAR(V1,G1) + CAR(M1,G1) = 2.0 + 3.0 = 5.0

7.	diode_area = 0, single-layer PWL(0) = 500, check PAR(V1,G1) = 2.0 <= 500, cum_layer PWL(0) = 1000, therefore check CAR(V1,G1) = 5.0 <= 1000

8.	PAR(M2,G1) = area(M2,1 + M2,2) / area(G1 + G2) = (4+5) / (1 + 2) = 3.0

9.	CAR(M2,G1) = PAR(M2,G1) + CAR(V1,G1) = 3.0 + 5.0 = 8.0

10.

diode_area = 0.5, single-layer PWL(0.5) = 1500, check PAR(M2,G1) = 3.0 <= 1500,
cum_layer PWL(0.5) = 4000, therefore check CAR(M2, G1) = 8.0 <= 4000

11.

PAR(V2,G1) = 10 x area(V2,1 + V2,2) / area(G1 + G2) = 10 x 0.2 / (1 + 2) = 0.67

12.

CAR(V2,G1) = PAR(V2,G1) + CAR(M2,G1) = 0.67 + 8.0 = 8.67

13.

diode_area = 0.5, single-layer PWL(0.5) = 1500, check PAR(V2,G1) = 0.67 <= 1500,
cum_layer PWL(0.5) = 4000, therefore check CAR(V2, G1) = 8.67 <= 4000

14.

PAR(M3,G1) = area(M3,1 + M3,2) / area(G1 + G2) = (6 + 9) / (1 + 2) = 5

15.

CAR(M3,G1) = PAR(M3,G1) + CAR(V2,G1) = 5 + 8.67 = 12.34

16.

diode_area = 0.5, single-layer PWL(0.5) = 1500, check PAR(M3,G1) = 5 <= 1500,
cum_layer PWL(0.5) = 4000, therefore check CAR(M3,G1) = 13.67 <= 4000

Example 2

The following cumulative rule is the same as the rule in Example 1, except it also subtracts the diff_area factor. Only the cumulative model is used.

ratio = [(metal_area + 10 x cut_area) - (100 x diff_area)] / gate_area

Every routing layer should include the following information:

ANTENNACUMROUTINGPLUSCUT ;

ANTENNAAREAMINUDIFF 100.0 ;

ANTENNACUMDIFFAREARATIO 1000 ;

Every cut layer should include the following information:

ANTENNAAREAFACTOR 10 ; #10.0 x cut area

ANTENNACUMROUTINGPLUSCUT ;

ANTENNAAREAMINUDIFF 100.0 ;

ANTENNACUMDIFFAREARATIO 1000 ;

For gate G1, the PARs and CARs are computed as follows:

1.	CAR(C,G1) = 10 x area(C1) / area(G1) = 10 x 0.1 / 1.0 = 2.0

This value is on the LEF PIN, as mentioned in Example 1.

2.	PAR(M1,G1) = area(M1,2) / area(G1) - (100 x diff_area) = (2 / 1) - (100 x 0) = 2.0

3.	CAR(M1,G1) = PAR(M1,G1) + PIN A's CAR(C,G1) PIN A's CAR(M1) = ANTENNAMAXAREACAR for LAYER M1 = 1.0 = 2.0 + 1.0 = 3.0

4.	Check CAR(M1,G1) = 3.0 <= 1000

5.	PAR(V1,G1) = [10 x area(V1,2 + V1,3) - (100 x diff_area)] / area(G1) = [(10 x .2) - (100 x 0)] / (1) = 2.0

6.	CAR(V1,G1) = PAR(V1,G1) + CAR(M1,G1) = 2.0 + 3.0 = 5.0

7.	Check CAR(V1,G1) = 5.0 <= 1000

8.	PAR(M2,G1) = [area(M2,1 + M2,2) - (100 x area(D1))] / area(G1 + G2) = [(4 + 5) - (100 x 0.5) / (1 + 2) = -13.67

9.	CAR(M2,G1) = PAR(M2,G1) + CAR(V1,G1) = -13.67 + 5.0 = -8.67, truncate to 0

10.

Check CAR(M2,G1) = 0 <= 1000

11.

PAR(V2,G1) = [(10 x area(V2,1 + V2,2)) - (100 x area(D1)] / area(G1 + G2)
= [(10 x 0.2) - (100 x 0.5)] / (1 + 2) = -16.0

12.

CAR(V2,G1) = PAR(V2,G1) + CAR(M2,G1) = -16.0 + 0 = -16.0, truncate to 0

13.

Check CAR(V2,G1) = 0 <= 1000

14.

PAR(M3,G1) = [area(M3,1 + M3,2) - (100 x area(D1))] / area(G1 + G2)
= [(6 + 9) - (100 x 0.5)] / (1 + 2) = -11.67

15.

CAR(M3,G1) = PAR(M3,G1) + CAR(V2,G1) = -11.67 + 0 = -11.67, truncate to 0

16.

Check CAR(M3,G1) = 0 <= 1000

Example 3

The following cumulative rule for metal layers includes a diffusion area factor added into the denominator of the ratio:

Single layer: metal_area / (gate_area + 2.0 x diff_area) <= 1000

Cumulative for the layer: metal_area / (gate_area + 2.0 x diff_area) <= 5000

Every metal layer should include the following information:

ANTENNAPLUSGATEDIFF 2.0 ;

ANTENNADIFFAREARATIO 1000 ;

ANTENNACUMDIFFAREARATIO 5000 ;

Note: The via area is ignored in this example. If an independent via model is needed, similar statements should be added to the via layers, which would be computed separately.

For gate G1, the PARs and CARs are computed as follows:

1.	PAR(M1,G1) = area(M1,2) / area(G1) = 2.0 / 1 = 2

2.	CAR(M1,G1) = PAR(M1,G1) = 2

3.	Check PAR(M1,G1) = 2 <= 1000, check CAR(M1,G1) = 2 <= 5000

4.	PAR(M2,G1) = area(M2,1 + M2,2) / [area(G1 + G2) + 2 x area(D1)] = (4 + 5) / [(1 + 2) + 2 x 0.5] = 2.25

5.	CAR(M2,G1) = CAR(M1,G1) + PAR(M2,G1) = 2 + 2.25 = 4.25

6.	Check PAR(M1,G1) = 2.25 <= 1000, check CAR(M1,G1) = 4.25 <= 5000

7.	PAR(M3,G1) = area(M3,1 + M3,2) / [area(G1 + G2) + 2 x area(D1)] = (6 + 9) / [(1 + 2) + 2 x 0.5] = 3.75

8.	CAR(M3,G1) = PAR(M3,G1) + CAR(M2,G1) = 3.75 + 4.25 = 8.0

9.	Check PAR(M1,G1) = 3.75 <= 1000, check CAR(M1,G1) = 8.0 <= 5000

Example 4

Assume a cumulative rule that includes a diffusion area reduction value and a routing ratio of 1000. The reduction value is 1.0 if the diff_area is less than 0.1, 0.2 if the diff_area equals 0.1, and decreases linearly to 0.1 if the diff_area equals 1.0. The reduction value remains 0.1 if the diff_area is greater than 1.0.

Every metal layer should include the following information:

ANTENNAAREADIFFREDUCEPWL ( ( 0.0 1.0 ) ( 0.0999 1.0 ) ( 0.1 0.2 )( 1.0 0.1 )

( 1000.0 0.1 ) ) ;" ;

ANTENNACUMDIFFAREARATIO 1000 ;

Note: The via area is ignored in this example. If an independent via model is needed, similar statements should be added to the via layers, which would be computed separately.

For gate G1, the PARs and CARs are computed as follows:

1.	Initial PAR(M1,G1) = area(M1,2) / area(G1) = 2.0 / 1 = 2

2.	diode_area = 0, PWL(0) = 1.0, therefore initial PAR(M1,G1) is multiplied by 1.0 to give PAR(M1,G1) = 2 x 1 = 2

3.	CAR(M1,G1) = PAR(M1,G1) = 2

4.	Check CAR(M1,G1) <= 1000, therefore check 2 <= 1000

5.	Initial PAR(M2,G1) = area(M2,1 + M2,2) / area(G1 + G2) = (4 + 5) / (1 + 2) = 3

6.	diode_area = 0.5, PWL(0.5) = 0.155, therefore initial PAR(M2,G1) is multiplied by 1.0 to give PAR(M2,G1) = 3 x 0.155 = 0.465

7.	CAR(M2,G1) = CAR(M1,G1) + PAR(M2,G1) = 2 + 0.465 = 2.465

8.	Check CAR(M2,G1) <= 1000, therefore check 2.465 <= 1000

9.	Initial PAR(M3,G1) = area(M3,1 + M3,2) / area(G1 + G2) = (6 + 9) / (1 + 2) = 5

10.

diode_area = 0.5, PWL(0.5) = 0.155, therefore initial PAR(M3,G1) is multiplied by 0.155
to give PAR(M3,G1) = 5 x 0.1555 = 0.775

11.

CAR(M3,G1) = PAR(M3,G1) + CAR(M2,G1) = 0.775 + 2.465 = 3.24

12.

Check CAR(M3,G1) <= 1000, therefore check 3.24 <= 1000

Example Using the Antenna Keywords

The following example is a portion of a LEF file that shows the antenna keywords for a process that has cumulative area ratio damage for metal and cut layers.

Assume you have the following antenna rules for your process:

1.	A maximum cumulative metal to gate area ratio of 1000

2.	If a diode of greater than .1 microns is connected to the metal, the maximum metal ratio is: ratio = diode_area x 2000 + 5000

3.	A maximum cumulative via to gate area ratio of 20

4.	If a diode of greater than .1 microns is connected to the via, the maximum via ratio is: ratio = diode_area x 200 + 100

The corresponding LEF file would include:

LAYER M1

TYPE ROUTING ;

...

ANTENNACUMAREARATIO 1000 ;

ANTENNACUMDIFFAREARATIO

PWL ( ( 0 1000 ) ( 0.099 1000 ) ( 0.1 5200 ) ( 100 205000 ) ) ;

ANTENNACUMAREARATIO 20 ;

ANTENNACUMDIFFAREARATIO

PWL ( ( 0 20 ) ( 0.099 20 ) ( 0.1 120 ) ( 100 20100 ) ) ;

END VIA1

A typical standard cell that has only M1 pins and routing inside of it would have:

ANTENNAGATEAREA .5 LAYER M1 ; # connects to 0.5 μm^2 poly gate

ANTENNAPARTIALMETALAREA 1.0 LAYER M1 ; # has 1.0 μm^2 M1 area.

# Note that it should not include the M1 pin area, just the M1 routing

# area that is not included in the PIN shapes. In many cases, all of the

# M1 routing is included in the PIN, so this value is 0, and not in the

# LEF at all.

ANTENNAMAXAREACAR 10.0 LAYER M1 ; # has 10.0 cumulative ratio so far.

# This value can include area from internal poly routing if poly routing

# damage is accumulated with the metal layers. It does not include

# the area of the M1 pin area, just the M1 routing area that is not

# included in the PIN shapes. If poly damage is not included, and all

# of the M1 routing is included in the PIN, this value will be 0, and

# not in the LEF at all.

ANTENNADIFFAREA .2 LAYER M1 ; # connects to 0.2 μm^2 difusion area

ANTENNAPARTIALMETALAREA 1.0 LAYER M1 ; # has 1.0 μm^2 M1 area

# No ANTENNAMAXAREACAR value because no internal poly gate is connected

...

END OUT

END INV1X

Using Antenna Diode Cells

Routers generally use one of two methods to fix process antenna violations:

Change the routing by breaking the metal layers into smaller pieces

Insert antenna diode cells to discharge the current

Changing the Routing

One method routers use to fix antenna violations is to limit the charge that is collected through the metal nodes exposed to the plasma. To do this, it goes up one layer or pushes the routing down one layer whenever the process antenna ratio exceeds the ratio set in the LEF file.

The router changes the routing by disconnecting nets with antenna violations and making the connections to higher metal layers instead. It does not make the connections to lower layers. This method works because the top metal layer always completes the connection from the gate to the output drain area of the driver, which is a diode that provides a discharge path.

Inserting Antenna Diode Cells

The second method routers use to repair antenna violations is to insert antenna diode cells in the design. The electrical charges on the metal that connects to the diodes is then discharged through the diode diffusion layer and substrate. The router inserts the diode cells automatically.

The following example shows a LEF definition of an antenna diode cell, with the CLASS CORE ANTENNACELL and ANTENNADIFFAREA defined:

MACRO antenna1

CLASS CORE ANTENNACELL ;

...

PIN ANT1

AntennaDiffArea 1.0 ;

PORT

LAYER metal1 ;

RECT 0.190 2.380 0.470 2.660 ;

END

END ANT1

END antenna1

Using DiffUseOnly

LEF defines only one value for ANTENNAAREAFACTOR and one value for ANTENNASIDEAREAFACTOR, with or without DIFFUSEONLY, per layer. If you specify more than one antenna area or side area factor for a layer, only the last one is used. The AREAFACTOR value lets you scale the value of the metal area. If you use the DIFFUSEONLY keyword, only metal attached to diffusion is scaled.

Suppose you have the following LEF file:

Figure C-21

In the figure,

The input pin H01 of GATE_M2_M3 connects the metal wires to metal1, metal2, and metal3 in sequence.

The ANTENNAAREAFACTOR 1.2 DIFFUSEONLY and ANTENNASIDEAREAFACTOR 1.4 DIFFUSEONLY apply to metal3 routing.

Prior to metal3 fabrication, there is no path to the diffusion diode. This causes the default factor of 1.0 to apply to the metal1 and metal2 segments shown when calculating PARs.

Calculations for Hierarchical Designs

The following section illustrates computation of antenna ratios for hierarchical designs.

LEF and DEF Keywords for Hierarchical Designs


If the keyword ends with ...	It refers to ...	Examples
area sideArea	Drawn area or side area of the metal wires. Measured in square microns.	ANTENNAPARTIALCUTAREA ANTENNAPARTIALMETALAREA ANTENNAPARTIALMETALSIDEAREA ANTENNAPINDIFFAREA ANTENNAPINGATEAREA ANTENNAPINPARTIALCUTAREA
CAR	Relationship the router is calculating CAR is used in keywords for cumulative antenna ratio.	ANTENNAMAXAREACAR ANTENNAMAXCUTCAR ANTENNAMAXSIDEAREACAR ANTENNAPINMAXAREACAR ANTENNAPINMAXCUTCAR ANTENNAPINMAXSIDEAREACAR

Design Example

Figure C-22 represents a macro block. This block can be a custom hard block or part of a bottom-up hierarchical flow. The resulting PAE values will be the same in either case. In the example,

Gates G₁, G₂, G₃, and G₄ are the same size.

Node N_1,3 is larger than node N_1,2.

Vias (cuts) are all the same size.

The I/O pin is on metal3.

The area of diffusion for D₁ is area(Diff₁).

The area of diffusion for D₂ is area(Diff₂).

The area of the cut layer that connects node N_3,1 and node N_4,2 is area(N_C34,1).

Any damage from the poly layer or poly-to-metal1 via is ignored.

Figure C-22

Relevant Metal Areas

The relevant metal area for PAE calculations is the partial metal drawn area and side area connected directly to the I/O pin on the inside of the macro on the specified layer.

Only the same metal layer as the I/O pin or above is needed for PAR calculations in hierarchical designs.

Do not include the drawn area or side area of the I/O pin in the area calculations for the block, because the router includes these areas in the calculations for the upper level. Only the internal routing area that is not part of the I/O pin should be included.

For the design in the figure above, you must specify values for the following metal areas in the LEF file:

ANTENNAPARTIALMETALAREA area(N_3,2) LAYER Metal3 ;

ANTENNAPARTIALMETALAREA area(N_4,2) LAYER Metal4 ;

ANTENNAPARTIALMETALSIDEAREA sideArea(N_3,2) LAYER Metal3 ;

ANTENNAPARTIALMETALSIDEAREA sideArea(N_4,2) LAYER Metal4 ;

You do not need to specify an ANTENNAPARTIALMETALAREA or ANTENNAPARTIALSIDEMETALAREA for any layer lower than metal3 because the I/O pin is on metal3; that is, there is no connection outside the block until metal3 is processed.